Huawei Unveils LogicFolding 3D Chips Bypassing EUV Dependency

Can a new 3D architecture truly challenge the reliance on EUV lithography? Huawei believes so, as it introduced its innovative LogicFolding architecture and the Tau (τ) scaling law, promising a 55% superior transistor density compared to conventional planar designs. On May 25, 2026, He Tingbo, president of Huawei's semiconductor department and a board member, unveiled these advancements at the IEEE ISCAS conference in Shanghai, explicitly designed to bypass the need for ASML's extreme ultraviolet (EUV) lithography machines.

This ambitious strategy targets achieving a density equivalent to a 1.4-nanometer process by 2031, not through actual etching at that fineness, but via a sophisticated 3D architectural design. Consumers can anticipate the first Kirin chips featuring LogicFolding to arrive in fall 2026. The announcement immediately stirred the market, with the stock of Chinese foundry SMIC jumping 7.6% in Hong Kong on the day of the news, as reported by CNBC.

"A stacked or folded design can produce effective density gains, but it does not mean Huawei has solved the full process, yield, power, thermal, and device-performance problems associated with true 1.4 nm-class manufacturing."
— Paul Triolo, DGA Group, in an interview with CNBC

Huawei's theoretical proposal aims to replace Moore's law's geometric scaling with a temporal scaling, where the optimization variable becomes the signal propagation delay across the entire computing stack. While the industry traditionally focused on reducing etching pitch—a purely physical metric—the Tau (τ) quantity proposed by Huawei targets the time a signal takes to traverse a logical chain, whether organized flat or in relief. Huawei claims to have designed and mass-produced 381 chips based on this principle over the past six years, though this claim remains self-declared and lacks external academic validation as of May 25, 2026.

According to Huawei, as reported by CNBC on May 25, 2026, the roadmap projects extending LogicFolding to Ascend chips by 2030. These are presented as domestic substitutes for Nvidia's training GPUs, which are banned from export to China. This timeline is significant: a report published by the Information Technology and Innovation Foundation in October 2025 suggests that U.S. export controls have paradoxically stimulated Huawei's internal capabilities, forcing the group to independently rebuild competencies that TSMC provided until 2020.

The LogicFolding architecture involves stacking the active layers of a logic circuit in three dimensions, which shortens electrical paths and maximizes transistor density by ground projection without relying on ASML's EUV lithography machines. The logic gain doesn't concern etching fineness, which is still limited by the equipment accessible to Huawei and foundry SMIC. Instead, the additional density is achieved by multiplying transistor levels above the same silicon footprint, with the etching pitch remaining unchanged.

Therefore, the claimed equivalence for 2031 with a 1.4 nm process is an effect of counting by ground projection, not the physical ability to trace patterns at that resolution. Paul Triolo, technology lead for Asia and the Americas at DGA Group, nuanced the scope of the announcement in an interview with CNBC on May 25, 2026. He noted that while a stacked or folded design can produce effective density gains, it does not mean Huawei has solved the full process, yield, power, thermal, and device-performance problems associated with true 1.4 nm-class manufacturing. No public data on yield, consumption, or thermal performance accompanied the announcement at this stage.

The 3D stacking of active layers is not an innovation unique to Huawei. Several Western and Korean foundries and designers, including Samsung, TSMC, and Intel, have been deploying comparable 3D stacking approaches for years, driven by commercial competitiveness rather than circumventing export sanctions. The specificity of LogicFolding lies less in the architectural idea itself than in the critical context in which it is being mobilized: that of a publisher cut off since 2020 from leading Western foundries and deprived of access to ASML's lithography machines. This move is part of a broader Chinese dynamic toward autonomy in the computing chain, with a clear political signal being Beijing's summoning of Nvidia in July 2025 regarding H20 chips, reflecting China's desire to extricate itself from a dependence considered a security risk.

The institutional authority of He Tingbo, who simultaneously holds positions as board director, president of the Scientist Committee, director of the ITMT (Information Technology Management Team), and president of the semiconductor department (HiSilicon), underscores the strategic importance of this development. HiSilicon, Huawei's design subsidiary, relied on TSMC until 2020. The Taiwanese foundry interrupted this relationship following the extraterritorial extension of US sanctions on semiconductor exports, forcing Huawei to rebuild its design chain with SMIC for production and invest massively in its architectural design. The choice of the IEEE ISCAS platform in Shanghai to present the τ law positions this reconstruction within the international academic register, rather than mere corporate communication, marking a significant step in China's pursuit of technological self-sufficiency.